The present invention relates to access control to main storage devices on a plurality of subsystems which constitutes a a data processing system and each of which has at least one instruction processor, at least one input/output device and at least one main storage device.
For example, a conventional data processing system is constituted by connecting 1-2 instruction processors (IP), a main storage device (MS device) and 1-4 input/output processors (IOP) through a system bus. Bus connection is used in this type data processing system because the number of interface lines between devices can be reduced greatly compared with the style in which local pass lines are provided between devices. In general, LSI improved in the degree of integration more greatly in recent years is used in this type data processing system, but the increase of the number of interface pins in LSI is relatively small compared with the remarkable improvement in the degree of integration. Accordingly, it is considered that importance of using such interface pins effectively, that is, importance of bus connecting means, will become larger in the field of this type data processing system hereafter.
On the other hand, a method of covering a performance range (inclusive of storage capacity range) beyond a conventional limit by connecting a plurality of data processing systems (called "subsystems") has appeared recently to answer the needs of improvement in system performance.
A method for facilitating the flexible change of system configuration by connecting a plurality system controllers (SC) described in Japanese Patent Publication JP-B-61-49706 which corresponds to U.S. patent application Ser. No. 973,466 filed Dec. 26, 1978 is known as this type prior art. In this method, table information that indicates the configuration of main storage devices with respect to the partial address space divided from absolute address space into the some unit is provided, so that not only the assignment of storage devices as to whether there is any storage device assigned for the address or as to what is a storage device assigned for the address can be known by reference to the table information at the time of reference of main storage device but data on a corresponding storage device can be referred to by using the assignment information. The data processing system using this method is a data processing system having buss lines provided between IP and SC and between SC and storage device with respect to the IP and the storage devices (Prior Art Example 1).
As another conventional technique, a distributed processing system multiplexed by connecting a plurality of subsystems through bus extender and extension bus has been disclosed in Japanese Patent Application Laid-Open No. JP-A-61-26169. Each of the subsystems constitutes a closed data processing system, so that ordinarily processing is made within the subsystem per se but reliability of the system can be improved through shifting the processing to another subsystem of the multiplexed system by using a method for communication between subsystems at extraordinary time of accidents or the like. Information such as transmission-side subsystem identification number/device number and reception-side subsystem identification number/device number is set in bus transfer information to coherently supporting communication between devices (such as IP, IOP and MS device) on the plurality of subsystems operating concurrently, so that access can reach the target device on the target subsystem on the basis of the information. Access to an MS device and communication between subsystems are made by one interface. In the case of access to a common MS device or in the case of access to an MS device on one of the subsystems, each of the data processing subsystems sets the subsystem identification number (subsystem identification number X of a common subsystem or subsystem identification number of an inner subsystem) in the REN portion of address pass format A on the basis of an address capacity decomposing instruction prepared in the data processing subsystem. In the Japanese Patent Application Laid-Open No. JP-A-61-26169, there is no description of access to outer subsystems (Prior Art Example 2).
As a further conventional technique, there is a parallel processing system improved in processing capacity by connecting a plurality of subsystems through switching interface circuits and butterfly switching circuits in TC2000 released on market by BBN Advanced Computer Inc. The scale of the data processing system is extended by using devices such as IP, IOP and MS devices on a plurality (8-504) of subsystems through a common OS, to thereby answer the needs of improvement in processing capacity, see Digest of Technical Papers of COMPCON, Spring, 1991, pp. 46-50. In TC2000, the system is formed so as to be suitable for parallel processing, so that address space formed by connecting memories on the plurality of subsystems is divided into local address space peculiar to each subsystem and common address space on the whole of the system (Prior Art Example 3).
Some conventional system has a work memory. For example, the system using the method described in Prior Art Example 1 can have a work memory provided in SC.